1. Field of the Invention
The present invention relates to suppressing sub-threshold leakage by under-driving transistors in their off state.
2. Discussion of the Related Art
Integrated circuits can include hundreds, thousands, or even millions of transistors. Each of these transistors can be in either an on (i.e., conducting) state or an off (i.e., non-conducting) state. Ideally, in an off state, a transistor would have zero power dissipation. Unfortunately, some static power dissipation in an integrated circuit can occur due to sub-threshold leakage current in these off transistors.
Some integrated circuits are particularly susceptible to such static power dissipation. For example, due to shrinking transistor dimensions, supply voltages, and threshold voltages, the sub-threshold leakage current in standard programmable logic devices (PLDs) has been increasing rapidly. In fact, at the current rate of increase, sub-threshold leakage current could quickly become the primary source of power dissipation in PLDs. For some PLDs that provide high power applications, high leakage power can lead to increased on-chip heating, thereby increasing the design and implementation costs of heat management. For other PLDs that use low-cost packaging, high leakage power can overtax the generally poor thermal qualities of such packaging. For yet other PLDs where minimizing usage of battery resources is critical, high leakage power prevents the use of such PLDs in various consumer products (e.g., wireless and handheld devices). Consequently, a need arises for techniques to reduce sub-threshold leakage current in PLDs.